Flip-flop circuits, including edge-triggered toggle flip-flops, are used as building blocks in many digital systems including counters, parity detectors, and registers. In response to each positive/negative edge of an input, usually referred to as the clock, the flip-flop changes its state: It toggles from a ‘0’ to a ‘1’, or from a ‘1’ to a ‘0’.
The prior art has used a number of techniques to avoid constant oscillatory behavior after the input edge has passed. Thus, for example, conventional toggle flip flops are configured so that each edge of a toggle input generates a brief input pulse that is of just the right duration so that the flip flop has sufficient time to change state only once. This strategy proves unreliable, since it relies on a high degree of accuracy in pulse timing. Alternatively, two bistable elements are sometimes configured in a “master-slave” feedback-loop configuration such that one bistable element is written on one phase of the clock signal while the other holds its state and vice versa. This second strategy is reliable but inefficient in its use of circuit area in integrated circuit (IC) chip implementations, since it requires two bistable elements and a number of logic gates for its operation.